Notes

// Sequence Detector
module SequenceDetector(
input clk, reset,
input X,
output reg Z
);

reg [3:0] state;

always @(posedge clk or posedge reset) begin
if (reset) begin
state <= 4'b0000;
Z <= 0;
end
else begin
case(state)
4'b0000: if (X) state <= 4'b0001;
4'b0001: if (!X) state <= 4'b0010;
4'b0010: if (!X) state <= 4'b0011;
4'b0011: if (X) state <= 4'b0100;
4'b0100: begin
if (X) begin
state <= 4'b0001;
Z <= 1;
end
else state <= 4'b0000;
end
default: state <= 4'b0000;
endcase
end
end

endmodule

// Multi-function Register
module MultiFunctionRegister(
input clk, reset,
input S1, S0,
input [1:0] data_in,
output reg [1:0] data_out
);

always @(posedge clk or posedge reset) begin
if (reset) begin
data_out <= 2'b00;
end
else begin
if (S1 == 0 && S0 == 1) data_out <= {data_out[0], data_out[1]};
else if (S1 == 1 && S0 == 0) data_out <= {data_out[1], data_out[0]};
else if (S1 == 1 && S0 == 1) data_out <= data_in;
end
end

endmodule