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Modulation classification is one of the key tasks for communications systems monitoring, management, and control for addressing technical issues, including spectrum awareness, adaptive transmissions, and interference avoidance. Recently, deep learning (DL)-based modulation classification has attracted significant attention due to its superiority in feature extraction and classification accuracy. In DL-based modulation classification, one major challenge is to preprocess a received signal and represent it in a proper format before feeding the signal into deep neural networks. This article provides a comprehensive survey of the state-of-the-art DL-based modulation classification algorithms, especially the techniques of signal representation and data preprocessing utilized in these algorithms. Since a received signal can be represented by either features, images, sequences, or a combination of them, existing algorithms of DL-based modulation classification can be categorized into four groups and are reviewed accordingly in this article. Furthermore, the advantages as well as disadvantages of each signal representation method are summarized and discussed.For systems with irregular (asymmetric and positively-negatively alternating) constraints being imposed/removed during system operation, there is no uniformly applicable control method. In this work, a control design framework is established for uncertain pure-feedback systems subject to the aforementioned constraints. By introducing a novel transformation function and with the help of auxiliary constraining boundaries, the original output-constrained system is augmented to unconstrained one. Unknown nonlinearity is approximated by neural networks (NNs) with not only neural weight updating but also activation online adjustment. The resultant control scheme is able to deal with constraints imposed or removed at some time moments during system operation without the need for altering control structure. ZEN-3694 solubility dmso When applied to high-speed trains, the developed control scheme ensures position tracking under speed constraints, simulation demands, and confirms the effectiveness of the proposed method.The purpose of this article is to present a novel backstepping-based adaptive neural tracking control design procedure for nonlinear systems with time-varying state constraints. The designed adaptive neural tracking controller is expected to have the following characters under its action 1) the designed virtual control signals meet the constraints on the corresponding virtual control states in order to realize the backstepping design ideal and 2) the output tracking error tends to a sufficiently small neighborhood of the origin with the prescribed finite time and accuracy level. By combining the barrier Lyapunov function approach with the adaptive neural backstepping technique, a novel adaptive neural tracking controller is proposed. It is shown that the constructed controller makes sure that the output tracking error converges to a small neighborhood of the origin with the prespecified tracking accuracy and settling time. Finally, the proposed control scheme is further tested by simulation examples.The human brain has evolved to perform complex and computationally expensive cognitive tasks, such as audio-visual perception and object detection, with ease. For instance, the brain can recognize speech in different dialects and perform other cognitive tasks, such as attention, memory, and motor control, with just 20 W of power consumption. Taking inspiration from neural systems, we propose a low-power neuromorphic hardware architecture to perform classification on temporal data at the edge. The proposed architecture uses a neuromorphic cochlea model for feature extraction and reservoir computing (RC) framework as a classifier. In the proposed hardware architecture, the RC framework is modified for on-the-fly generation of reservoir connectivity, along with binary feedforward and reservoir weights. Also, a large reservoir is split into multiple small reservoirs for efficient use of hardware resources. These modifications reduce the computational and memory resources required, thereby resulting in a lower power budget. The proposed classifier is validated for speech and human activity recognition (HAR) tasks. We have prototyped our hardware architecture using Intel's cyclone-10 low-power series field-programmable gate array (FPGA), consuming only 4790 logic elements (LEs) and 34.9-kB memory, making it a perfect candidate for edge computing applications. Moreover, we have implemented a complete system for speech recognition with the feature extraction block (cochlea model) and the proposed classifier, utilizing 15,532 LEs and 38.4-kB memory. By using the proposed idea of multiple small reservoirs along with on-the-fly generation of reservoir binary weights, our architecture can reduce the power consumption and memory requirement by order of magnitude compared to existing FPGA models for speech recognition tasks with similar complexity.We propose a novel network pruning approach by information preserving of pretrained network weights (filters). Network pruning with the information preserving is formulated as a matrix sketch problem, which is efficiently solved by the off-the-shelf frequent direction method. Our approach, referred to as FilterSketch, encodes the second-order information of pretrained weights, which enables the representation capacity of pruned networks to be recovered with a simple fine-tuning procedure. FilterSketch requires neither training from scratch nor data-driven iterative optimization, leading to a several-orders-of-magnitude reduction of time cost in the optimization of pruning. Experiments on CIFAR-10 show that FilterSketch reduces 63.3% of floating-point operations (FLOPs) and prunes 59.9% of network parameters with negligible accuracy cost for ResNet-110. On ILSVRC-2012, it reduces 45.5% of FLOPs and removes 43.0% of parameters with only 0.69% accuracy drop for ResNet-50. Our code and pruned models can be found at https//github.com/lmbxmu/FilterSketch.This article investigates the synchronization of fractional-order multi-weighted complex networks (FMWCNs) with order α∈ (0,1). A useful fractional-order inequality t₀C Dtα V(x(t))≤ -μ V(x(t)) is extended to a more general form t₀C Dtα V(x(t))≤ -μ Vɣ(x(t)),ɣ∈ (0,1], which plays a pivotal role in studies of synchronization for FMWCNs. However, the inequality t₀C Dtα V(x(t))≤ -μ Vɣ(x(t)),ɣ∈ (0,1) has been applied to achieve the finite-time synchronization for fractional-order systems in the absence of rigorous mathematical proofs. Based on reduction to absurdity in this article, we prove that it cannot be used to obtain finite-time synchronization results under bounded nonzero initial value conditions. Moreover, by using feedback control strategy and Lyapunov direct approach, some sufficient conditions are presented in the forms of linear matrix inequalities (LMIs) to ensure the synchronization for FMWCNs in the sense of a widely accepted definition of synchronization. Meanwhile, these proposed sufficient results cannot guarantee the finite-time synchronization of FMWCNs.
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