Notes

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-- Company:
-- Engineer:
--
-- Create Date: 11.11.2024 09:03:09
-- Design Name:
-- Module Name: TOP_MODULE - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity TOP_MODULE is
Port ( IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
IN3 : in STD_LOGIC;
IN4 : in STD_LOGIC;
OUT3 : out STD_LOGIC);
end TOP_MODULE;

architecture Behavioral of TOP_MODULE is
COMPONENT projecto is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end COMPONENT;

COMPONENT ORGATE is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
X : out STD_LOGIC);
end COMPONENT;
signal OUT1,OUT2:std_logic;


begin
G1:projecto port map (A=>IN1, B=>IN2, X=>OUT1);
G2:projecto port map (A=>IN3, B=>IN4, X=>OUT2);
G3:ORGATE port map (A=>OUT1, B=>OUT2, X=>OUT3);

end Behavioral;

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library IEEE;
use IEEE.Std_logic_1164.all;
use IEEE.Numeric_Std.all;

entity TOP_MODULE_tb is
end;

architecture bench of TOP_MODULE_tb is

component TOP_MODULE
Port ( IN1 : in STD_LOGIC;
IN2 : in STD_LOGIC;
IN3 : in STD_LOGIC;
IN4 : in STD_LOGIC;
OUT3 : out STD_LOGIC);
end component;

signal IN1: STD_LOGIC;
signal IN2: STD_LOGIC;
signal IN3: STD_LOGIC;
signal IN4: STD_LOGIC;
signal OUT3: STD_LOGIC;

begin

uut: TOP_MODULE port map ( IN1 => IN1,
IN2 => IN2,
IN3 => IN3,
IN4 => IN4,
OUT3 => OUT3 );

stimulus: process
begin
-- Initialization code
IN1 <= '0';
IN2 <= '0';
IN3 <= '0';
IN4 <= '0';

-- Test case 1: Apply inputs 00, 00
IN1 <= '0'; IN2 <= '0'; IN3 <= '0'; IN4 <= '0';
wait for 10 ns; -- Wait for 10 ns

-- Test case 2: Apply inputs 01, 01
IN1 <= '0'; IN2 <= '1'; IN3 <= '0'; IN4 <= '1';
wait for 10 ns;

-- Test case 3: Apply inputs 10, 10
IN1 <= '1'; IN2 <= '0'; IN3 <= '1'; IN4 <= '0';
wait for 10 ns;

-- Test case 4: Apply inputs 11, 11
IN1 <= '1'; IN2 <= '1'; IN3 <= '1'; IN4 <= '1';
wait for 10 ns;

-- Test case 5: Apply random values to test robustness
IN1 <= '0'; IN2 <= '1'; IN3 <= '1'; IN4 <= '0';
wait for 10 ns;

-- End the simulation
assert false report "Testbench finished" severity failure;
end process;

end;