Notes

----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:11:35 10/23/2015
-- Design Name:
-- Module Name: traffic_light - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity traffic_light is
port( clk , reset : in std_logic ;
red,yellow,green : out std_logic);
end traffic_light;

architecture Behavioral of traffic_light is
signal count : integer :=0;
begin
process(clk,reset) is
begin
if( clk'event and clk ='1') then
if(reset = '1') then
count <= 0;
red <= '1';
yellow <= '0';
green <= '0';
end if;

if( count = 5) then
red <= '0';
yellow <= '1';
green <= '0';
elsif( count = 10) then
red <= '0';
yellow <= '0';
green <= '1';
elsif( count = 15) then
red <= '1';
yellow <= '0';
green <= '0';
end if;
count <= count + 1;
if ( count = 16 ) then
count <= 0;
end if;
end if;
end process;

end Behavioral;