Notes

--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:05:44 11/02/2015
-- Design Name:
-- Module Name: C:/Xilinx/7thsem/traffic_contr/test_traffic.vhd
-- Project Name: traffic_contr
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: traffic_light
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;

ENTITY test_traffic IS
END test_traffic;

ARCHITECTURE behavior OF test_traffic IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT traffic_light
PORT(
clk : IN std_logic;
reset : IN std_logic;
red : OUT std_logic;
yellow : OUT std_logic;
green : OUT std_logic
);
END COMPONENT;


--Inputs
signal clk : std_logic := '0';
signal reset : std_logic := '0';

--Outputs
signal red : std_logic;
signal yellow : std_logic;
signal green : std_logic;


BEGIN

-- Instantiate the Unit Under Test (UUT)
uut: traffic_light PORT MAP (
clk => clk,
reset => reset,
red => red,
yellow => yellow,
green => green
);

-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for 20 ns;
clk <= '1';
wait for 20 ns;
end process;


-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for 50 ns;
reset <= '0';
wait for 5000 ns;
end process;

END;