Notes

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity D_FF is
PORT ( D,CLOCK,R : IN STD_LOGIC;
Q : OUT STD_LOGIC);
end D_FF;

architecture Behavioral of D_FF is
begin
PROCESS (CLOCK,R)
begin
IF (R='0') THEN
Q<='1';
ELSIF (CLOCK'EVENT AND CLOCK='1') THEN
Q<=D;
END IF;
END PROCESS;
end Behavioral;
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity UP_DOWN_COUNTER is
PORT ( CLOCK,RESET,DOWN : IN STD_LOGIC;
A0,A1,A2,A3 : OUT STD_LOGIC);
end UP_DOWN_COUNTER;

architecture Behavioral of UP_DOWN_COUNTER is
COMPONENT D_FF is
PORT ( D,CLOCK,R : IN STD_LOGIC;
Q : OUT STD_LOGIC);
end COMPONENT;
SIGNAL Q0,Q1,Q2,Q3,QP0,QP1,QP2,QP3 : STD_LOGIC;
SIGNAL CLK1,CLK2,CLK3 : STD_LOGIC;
begin
QP0<=NOT Q0; QP1<=NOT Q1; QP2<=NOT Q2; QP3<=NOT Q3;
CLK1 <= DOWN XOR QP0; CLK2 <= DOWN XOR QP1; CLK3 <= DOWN XOR QP2;
DFF0 : D_FF PORT MAP (QP0,CLOCK,RESET,Q0);
DFF1 : D_FF PORT MAP (QP1,CLK1,RESET,Q1);
DFF2 : D_FF PORT MAP (QP2,CLK2,RESET,Q2);
DFF3 : D_FF PORT MAP (QP3,CLK3,RESET,Q3);
A0<=Q0; A1<=Q1; A2<=Q2; A3<=Q3;
end Behavioral;