Notes

**##And gate
library ieee;
use ieee.std_logic_1164.all;

entity andgate is
port(
a:in std_ulogic;
b: in std_ulogic;
c: out std_ulogic
);
end andgate;

architecture behavior of andgate is
begin

c <= a and b;

end behavior;
** ## AND GATE TESTBENCH
library ieee;
use ieee.std_logic_1164.all;

entity andgate_tb is
---> no content
end andgate_tb;

architecture test of andgate_tb is
component andgate
port(
a,b: in std_logic;
c: out std_logic
);
end component;

signal ak,bk,ck: std_logic;

begin

and_gate: andgate port map(a=>ak, b=>bk, c=>ck);

process begin

ak <= '0';
bk <= '0';
wait for 1 ns;

ak <= '0';
bk <= '1';
wait for 1 ns;

ak <= '1';
bk <= '0';
wait for 1 ns;

ak <= '1';
bk <= '1';
wait for 1 ns;

assert false report "Completed successfully";
wait;
end process;
end test;
**## FULL ADDER
library ieee;
use ieee.std_logic_1164.all;

entity fa is
port(
a: in std_ulogic;
b: in std_ulogic;
cin: in std_ulogic;
cout: out std_ulogic;
s: out std_ulogic
);
end fa;

architecture behave of fa is
begin
s <= (a xor b) xor cin;
cout <= ((a xor b) and cin) or (a and b);
end behave;

**##FULL ADDER TEST BENCH
library ieee;
use ieee.std_logic_1164.all;

entity fa_testbench is
end fa_testbench;

architecture test of fa_testbench is
component fa
port(
a: in std_ulogic;
b: in std_ulogic;
cin: in std_ulogic;
cout: out std_ulogic;
s: out std_ulogic
);
end component;

signal ain, bin, cin, cout, sum : std_logic;

begin
full_adder: fa port map (a => ain, b => bin, cin => cin, cout => cout, s => sum);

process begin

ain <= '0';
bin <= '0';
cin <= '0';
wait for 1 ns;

ain <= '0';
bin <= '0';
cin <= '1';
wait for 1 ns;

ain <= '0';
bin <= '1';
cin <= '0';
wait for 1 ns;

ain <= '0';
bin <= '1';
cin <= '1';
wait for 1 ns;

ain <= '1';
bin <= '0';
cin <= '0';
wait for 1 ns;

ain <= '1';
bin <= '0';
cin <= '1';
wait for 1 ns;

ain <= '1';
bin <= '1';
cin <= '0';
wait for 1 ns;

ain <= '1';
bin <= '1';
cin <= '1';
wait for 1 ns;

assert false report "Reached end of test";
wait;
end process;
end test;
**## HALF ADDER
library ieee;
use ieee.std_logic_1164.all;
entity ha is
port
(
a: in std_ulogic;
b: in std_ulogic;
s: out std_ulogic;
c: out std_ulogic
);
end ha;

architecture behave of ha is
begin
s <= a xor b;
c <= a and b;
end behave;
**## HALF ADDER TEST BENCH
library ieee;
use ieee.std_logic_1164.all;
entity ha_tb is
end ha_tb;

architecture test of ha_tb is
component ha
port
(
a: in std_ulogic;
b: in std_ulogic;
c: out std_ulogic;
s: out std_ulogic
);
end component;
signal a,b,s,c: std_logic;
begin
half_adder: ha port map (a=>a, b=>b ,c=>c, s=>s);
process begin
a <= '0';
b <= '0';
wait for 1 ns;
a <= '0';
b <= '1';
wait for 1 ns;
a <= '1';
b <= '0';
wait for 1 ns;
a <= '1';
b <= '1';
wait for 1 ns;

assert false report "Reached end of test";
wait;
end process;
end test;
**## NAND GATE
library ieee;
use ieee.std_logic_1164.all;

entity nandgate is
port(
a,b:in std_logic;
c: out std_logic
);
end nandgate;

architecture behavior of nandgate is
begin

c <= not (a and b);

end behavior;
**## NAND GATE TEST BENCH
library ieee;
use ieee.std_logic_1164.all;

entity nandgate_testbench is
---> no content
end nandgate_testbench;

architecture test of nandgate_testbench is
component nandgate
port(
a,b: in std_logic;
c: out std_logic
);
end component;

signal a,b,c: std_logic;

begin

nand_gate: nandgate port map(a=>a, b=>b, c=>c);

process begin

a <= '0';
b <= '0';
wait for 1 ns;

a <= '0';
b <= '1';
wait for 1 ns;

a <= '1';
b <= '0';
wait for 1 ns;

a <= '1';
b <= '1';
wait for 1 ns;

assert false report "Completed successfully";
wait;
end process;
end test;
**## NOT GATE
library ieee;
use ieee.std_logic_1164.all;

entity notgate is
port(
a: in std_logic;
b: out std_logic
);
end notgate;

architecture behavior of notgate is
begin

b <= not a;

end behavior;
**## NOT GATE TEST BENCH
library ieee;
use ieee.std_logic_1164.all;

entity notgate is
port(
a: in std_logic;
b: out std_logic
);
end notgate;

architecture behavior of notgate is
begin

b <= not a;

end behavior;

**## OR GATE
library ieee;
use ieee.std_logic_1164.all;

entity orgate is
port(
a,b:in std_logic;
c: out std_logic
);
end orgate;

architecture behavior of orgate is
begin

c <= a or b;

end behavior;


**## ORGATE TEST BENCH
library ieee;
use ieee.std_logic_1164.all;

entity orgate_testbench is
---> no content
end orgate_testbench;

architecture test of orgate_testbench is
component orgate
port(
a,b: in std_logic;
c: out std_logic
);
end component;

signal a,b,c: std_logic;

begin

or_gate: orgate port map(a=>a, b=>b, c=>c);

process begin

a <= '0';
b <= '0';
wait for 1 ns;

a <= '0';
b <= '1';
wait for 1 ns;

a <= '1';
b <= '0';
wait for 1 ns;

a <= '1';
b <= '1';
wait for 1 ns;

assert false report "Successfully Completed !";
wait;
end process;
end test;