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#include <stdio.h> // for stderr
#include <stdlib.h> // for exit()
#include "types.h"
#include "utils.h"
#include "riscv.h"

void execute_rtype(Instruction, Processor *);
void execute_itype_except_load(Instruction, Processor *);
void execute_branch(Instruction, Processor *);
void execute_jal(Instruction, Processor *);
void execute_jalr(Instruction, Processor *);
void execute_load(Instruction, Processor *, Byte *);
void execute_store(Instruction, Processor *, Byte *);
void execute_ecall(Processor *, Byte *);
void execute_lui(Instruction, Processor *);
void execute_auipc(Instruction, Processor *);

void execute_instruction(uint32_t instruction_bits, Processor *processor,Byte *memory) {
Instruction instruction = parse_instruction(instruction_bits); // Look in utils.c
switch(instruction.opcode) {
case 0x33:
/* YOUR CODE HERE */
execute_rtype(instruction, processor);
break;
case 0x13:
/* YOUR CODE HERE */
execute_itype_except_load(instruction, processor);
break;
case 0x3:
/* YOUR CODE HERE */
execute_load(instruction, processor, memory);
break;
case 0x67:
/* YOUR CODE HERE */
execute_itype_except_load(instruction, processor);
break;
case 0x23:
/* YOUR CODE HERE */
execute_store(instruction, processor, memory);
break;
case 0x63:
/* YOUR CODE HERE */
execute_branch(instruction, processor);
break;
case 0x37:
/* YOUR CODE HERE */
execute_lui(instruction, processor);
break;
case 0x17:
/* YOUR CODE HERE */
execute_auipc(instruction, processor);
break;
case 0x6F:
/* YOUR CODE HERE */
execute_jal(instruction, processor);
break;
case 0x73:
/* YOUR CODE HERE */
execute_ecall(processor, memory);
// didn't incr pc in execute_ecall
processor->PC += 4;
break;
default: // undefined opcode
handle_invalid_instruction(instruction);
exit(-1);
break;
}
}

/*
typedef struct {
Register R[32];
Register PC;
} Processor;
*/
void execute_rtype(Instruction instruction, Processor *processor) {
switch (instruction.rtype.funct3){
case 0x0:
/* YOUR CODE HERE */
switch(instruction.rtype.funct7) {
case 0x00:
// add
processor->R[instruction.rtype.rd] = (sWord)processor->R[instruction.rtype.rs1] + (sWord)processor->R[instruction.rtype.rs2];
processor->PC = processor->PC + 4;
break;
case 0x01:
// mul
processor->R[instruction.rtype.rd] = (sWord)processor->R[instruction.rtype.rs1] * (sWord)processor->R[instruction.rtype.rs2];
processor->PC += 4;
break;
case 0x20:
//sub
processor->R[instruction.rtype.rd] = ((sWord)processor->R[instruction.rtype.rs1]) - ((sWord)processor->R[instruction.rtype.rs2]);
processor->PC += 4;
break;
default: // undefined opcode
handle_invalid_instruction(instruction);
break;
}
break;
case 0x1:
/* YOUR CODE HERE */
switch(instruction.rtype.funct7) {
case 0x00:
// sll
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs1] << processor->R[instruction.rtype.rs2];
processor->PC += 4;
break;

case 0x01:
// mulh
processor->R[instruction.rtype.rd] = (sWord)((sDouble)((sWord)processor->R[instruction.rtype.rs1] * (sWord)processor->R[instruction.rtype.rs2]) >> 32) ;
processor->PC += 4;
break;

default: // undefined opcode
handle_invalid_instruction(instruction);
break;
}
break;

case 0x2:
/* YOUR CODE HERE */
// slt
processor->R[instruction.rtype.rd] = ((sWord)processor->R[instruction.rtype.rs1] < (sWord)processor->R[instruction.rtype.rs2]) ? 1 : 0;
processor->PC += 4;
break;
case 0x3:
/* YOUR CODE HERE */
switch(instruction.rtype.funct7) {
case 0x00:
//sltu
processor->R[instruction.rtype.rd] = (processor->R[instruction.rtype.rs1] < processor->R[instruction.rtype.rs2]) ? 1 : 0;
processor->PC += 4;
break;
case 0x01:
//mulhu
processor->R[instruction.rtype.rd] = (sWord)((sDouble)((sWord)processor->R[instruction.rtype.rs1] * (sWord)processor->R[instruction.rtype.rs2]) >> 32) ;
processor->PC += 4;
break;
default: // undefined opcode
handle_invalid_instruction(instruction);
break;
}
break;
/////////////////////////////
case 0x4:
/* YOUR CODE HERE */
switch(instruction.rtype.funct7) {
case 0x00:
//xor
processor->R[instruction.rtype.rd] = (processor->R[instruction.rtype.rs1]) ^ (processor->R[instruction.rtype.rs2]);
processor->PC += 4;
break;
case 0x01:
//div
processor->R[instruction.rtype.rd] = ((sWord)processor->R[instruction.rtype.rs1] / (sWord)processor->R[instruction.rtype.rs2]);
processor->PC += 4;
break;
default: // undefined opcode
handle_invalid_instruction(instruction);
break;
}
break;
case 0x5:
/* YOUR CODE HERE */
switch(instruction.rtype.funct7) {
case 0x00:
//srl
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs1] >> processor->R[instruction.rtype.rs2];
processor->PC += 4;
break;
case 0x01:
//divu
processor->R[instruction.rtype.rd] = ((sWord)processor->R[instruction.rtype.rs1] / (sWord)processor->R[instruction.rtype.rs2]);
processor->PC += 4;
break;
case 0x20:
//sra
processor->R[instruction.rtype.rd] = processor->R[instruction.rtype.rs1] >> instruction.itype.imm;
processor->PC += 4;
break;
default: // undefined opcode
handle_invalid_instruction(instruction);
break;
}
break;
case 0x6:
/* YOUR CODE HERE */
switch(instruction.rtype.funct7) {
case 0x00:
// or
processor->R[instruction.rtype.rd] = (processor->R[instruction.rtype.rs1]) | (processor->R[instruction.rtype.rs2]);
processor->PC += 4;
break;
case 0x01:
processor->R[instruction.rtype.rd] = ((sWord)processor->R[instruction.rtype.rs1]) % ((sWord)processor->R[instruction.rtype.rs2]);
processor->PC += 4;
break;
default: // undefined opcode
handle_invalid_instruction(instruction);
break;
}
break;
case 0x7:
/* YOUR CODE HERE */
switch(instruction.rtype.funct7) {
case 0x00:
//and
processor->R[instruction.rtype.rd] = (processor->R[instruction.rtype.rs1]) & (processor->R[instruction.rtype.rs2]);
processor->PC += 4;
break;
case 0x01:
//remu
processor->R[instruction.rtype.rd] = ((sWord)processor->R[instruction.rtype.rs1]) % ((sWord)processor->R[instruction.rtype.rs2]);
processor->PC += 4;
break;
default: // undefined opcode
handle_invalid_instruction(instruction);
break;
}
break;
default:
handle_invalid_instruction(instruction);
break;
}
}

void execute_itype_except_load(Instruction instruction, Processor *processor) {
switch (instruction.itype.funct3) {
case 0x0:
/* YOUR CODE HERE */
switch (instruction.opcode) {
case 0x13:
//addi
processor->R[instruction.itype.rd] = (sWord)(processor->R[instruction.itype.rs1]) + sign_extend_number(instruction.itype.imm, 12);
processor->PC += 4;
break;
case 0x67:
//jalr
execute_jalr(instruction, processor);
break;
default: // undefined opcode
handle_invalid_instruction(instruction);
break;
}
break;
case 0x1:
/* YOUR CODE HERE */
//slli (shift left logical immediate... doesn't need sign_extend_number)
processor->R[instruction.itype.rd] = processor->R[instruction.itype.rs1] << instruction.itype.imm;
processor->PC += 4;
break;
case 0x2:
/* YOUR CODE HERE */
//slti (set less than immediate)
processor->R[instruction.itype.rd] = ((sWord)processor->R[instruction.itype.rs1] < sign_extend_number(instruction.itype.imm, 12)) ? 1 : 0;
processor->PC += 4;
break;
case 0x3:
/* YOUR CODE HERE */
//sltiu
processor->R[instruction.itype.rd] = (processor->R[instruction.itype.rs1] < (instruction.itype.imm)) ? 1 : 0;
processor->PC += 4;
break;

case 0x4:
/* YOUR CODE HERE */
//xori
processor->R[instruction.itype.rd] = (processor->R[instruction.itype.rs1] ^ sign_extend_number(instruction.itype.imm, 12));
processor->PC += 4;
break;

case 0x5:
/* YOUR CODE HERE */
//imm is 12 bits
switch(instruction.itype.imm >> 10) {
case 0x0:
// srli
processor->R[instruction.itype.rd] = processor->R[instruction.itype.rs1] >> instruction.itype.imm;
processor->PC += 4;
break;
case 0x1:
// srai ?????????????
processor->R[instruction.itype.rd] = sign_extend_number((processor->R[instruction.itype.rs1] >> instruction.itype.imm), (32 - instruction.itype.imm));
/*
if (((processor->R[instruction.itype.rs1] >> instruction.itype.imm) & 1) == 1) {
processor->R[instruction.itype.rd] = 0xFFFFFFFF | val;
} else {
processor->R[instruction.itype.rd] = 0xFFFFFFFF | val;
}
*/
processor->PC += 4;

break;
default: // undefined opcode
handle_invalid_instruction(instruction);
break;
}
break;
case 0x6:
/* YOUR CODE HERE */
// ori
processor->R[instruction.itype.rd] = processor->R[instruction.itype.rs1] | sign_extend_number(instruction.itype.imm, 12);
processor->PC += 4;
break;

case 0x7:
/* YOUR CODE HERE */
//andi
processor->R[instruction.itype.rd] = processor->R[instruction.itype.rs1] & sign_extend_number(instruction.itype.imm, 12);
processor->PC += 4;
break;

default:
handle_invalid_instruction(instruction);
break;
}
}

void execute_ecall(Processor *p, Byte *memory) {

Register i;
// a0 and a1 are params of ecall
// when a0 is 1, ecall prints out whatever is in a1. (proj spec confirm))
// What do we switch on?
// fill in switch statement
switch(p->R[10]) {
case 1: // print an integer
printf("%d",p->R[11]);
break;
case 4: // print a string
for(i = p->R[11]; i < MEMORY_SPACE && load(memory, i, LENGTH_BYTE); i++) {
printf("%c",load(memory,i,LENGTH_BYTE));
}
break;
case 10: // exit
printf("exiting the simulatorn");
exit(0);
break;
case 11: // print a character
printf("%c",p->R[11]);
break;
default: // undefined ecall
printf("Illegal ecall number %dn", p->R[10]);
exit(-1);
break;
}
}

void execute_branch(Instruction instruction, Processor *processor) {
switch (instruction.sbtype.funct3) {
case 0x0:
/* YOUR CODE HERE */
// beq
//if ((processor->R[instruction.sbtype.rs1]) == (processor->R[instruction.sbtype.rs2]))
if (((sWord)processor->R[instruction.sbtype.rs1]) == ((sWord)processor->R[instruction.sbtype.rs2])) {
processor->PC += get_branch_offset(instruction);
}
else {
processor->PC += 4;
}
break;
case 0x1:
/* YOUR CODE HERE */
// bne
//if ((processor->R[instruction.sbtype.rs1]) != (processor->R[instruction.sbtype.rs2]))
if (((sWord)processor->R[instruction.sbtype.rs1]) != ((sWord)processor->R[instruction.sbtype.rs2])) {
processor->PC += get_branch_offset(instruction);
}
else {
processor->PC += 4;
}
break;
case 0x4:
/* YOUR CODE HERE */
// blt
//if ((processor->R[instruction.sbtype.rs1]) < (processor->R[instruction.sbtype.rs2]))
if (((sWord)(processor->R[instruction.sbtype.rs1])) < ((sWord)(processor->R[instruction.sbtype.rs2]))) {
processor->PC += get_branch_offset(instruction);
}
else {
processor->PC += 4;
}
break;

case 0x5:
/* YOUR CODE HERE */
// bge
//if ((processor->R[instruction.sbtype.rs1]) >= (processor->R[instruction.sbtype.rs2]))
if (((sWord)(processor->R[instruction.sbtype.rs1])) >= ((sWord)(processor->R[instruction.sbtype.rs2]))) {
processor->PC += get_branch_offset(instruction);
}
else {
processor->PC += 4;
}
break;
case 0x6:
/* YOUR CODE HERE */
// bltu ((brnach less than to unsigned))
//if ((processor->R[instruction.sbtype.rs1]) < (processor->R[instruction.sbtype.rs2]))
if (((Word)(processor->R[instruction.sbtype.rs1])) < ((Word)(processor->R[instruction.sbtype.rs2]))) {
processor->PC += sign_extend_number(get_branch_offset(instruction), 13);
//processor->PC += instruction;
}
else {
processor->PC += 4;
}
break;
case 0x7:
/* YOUR CODE HERE */
//bgeu (brnach greater than or equal to unsigned)
if (((Word)(processor->R[instruction.sbtype.rs1])) >= ((Word)(processor->R[instruction.sbtype.rs2]))) {
// if ((processor->R[instruction.sbtype.rs1]) >= (processor->R[instruction.sbtype.rs2]))
processor->PC += sign_extend_number(get_branch_offset(instruction), 13);
//processor->PC += instruction;
}
else {
processor->PC += 4;
}
break;
default:
handle_invalid_instruction(instruction);
break;
}
}

// load in rd
void execute_load(Instruction instruction, Processor *processor, Byte *memory) {
switch (instruction.itype.funct3) {
case 0x0:
/* YOUR CODE HERE */
// lb
processor->R[instruction.itype.rd] = sign_extend_number(load(memory, (processor->R[instruction.itype.rs1] + sign_extend_number(instruction.itype.imm, 12)), LENGTH_BYTE), 8);
processor->PC += 4;
break;
case 0x1:
/* YOUR CODE HERE */
// lh
processor->R[instruction.itype.rd] = sign_extend_number(load(memory, (processor->R[instruction.itype.rs1] + sign_extend_number(instruction.itype.imm, 12)), LENGTH_HALF_WORD), 16);
processor->PC += 4;
break;
case 0x2:
/* YOUR CODE HERE */
// lw
processor->R[instruction.itype.rd] = load(memory, (processor->R[instruction.itype.rs1] + sign_extend_number(instruction.itype.imm, 12)), LENGTH_WORD);
processor->PC += 4;
break;
case 0x4:
/* YOUR CODE HERE */
//lbu.. UNSIGNED
processor->R[instruction.itype.rd] = load(memory, processor->R[instruction.itype.rs1] + instruction.itype.imm, LENGTH_BYTE);
processor->PC += 4;
break;
case 0x5:
/* YOUR CODE HERE */
//lhu
processor->R[instruction.itype.rd] = load(memory, processor->R[instruction.itype.rs1] + instruction.itype.imm, LENGTH_HALF_WORD);
processor->PC += 4;
break;
default:
handle_invalid_instruction(instruction);
break;
}
}

// store in memory
void execute_store(Instruction instruction, Processor *processor, Byte *memory) {
switch (instruction.stype.funct3) {
case 0x0:
/* YOUR CODE HERE */
//sb ... address and word value... rs2's value goes into u3[rs1 + offset]
store(memory, processor->R[instruction.stype.rs1] + get_store_offset(instruction), LENGTH_BYTE, processor->R[instruction.stype.rs2]);
processor->PC += 4;
break;
case 0x1:
/* YOUR CODE HERE */
//sh
store(memory, processor->R[instruction.stype.rs1] + get_store_offset(instruction), LENGTH_HALF_WORD, processor->R[instruction.stype.rs2]);
processor->PC += 4;
break;
case 0x2:
/* YOUR CODE HERE */
//sw
store(memory, processor->R[instruction.stype.rs1] + get_store_offset(instruction), LENGTH_WORD, processor->R[instruction.stype.rs2]);
processor->PC += 4;
break;
default:
handle_invalid_instruction(instruction);
break;
}
}

void execute_jal(Instruction instruction, Processor *processor) {
/* YOUR CODE HERE */
// rd equals next line
processor->R[instruction.ujtype.rd] = (processor->PC + 4);
// jumping... problem was with no sign adjustment in get_jump_offset
processor->PC += get_jump_offset(instruction);
//processor->PC += 4;
}

void execute_jalr(Instruction instruction, Processor *processor) {
/* YOUR CODE HERE */
// rd equals next line
processor->R[instruction.itype.rd] = (processor->PC + 4);
// jumping with rs1 (green sheet eq)
processor->PC = processor->R[instruction.itype.rs1] + sign_extend_number((instruction.itype.imm), 12);
//get_jump_offset(instruction);
}

void execute_lui(Instruction instruction, Processor *processor) {
/* YOUR CODE HERE */
// lui (load upper imm): rd <- imm... remember shift 12 because imm[31:12]
// processor->R[instruction.utype.rd] is UNSIGNED
processor->R[instruction.utype.rd] = instruction.utype.imm << 12;
processor->PC += 4;
}

void execute_auipc(Instruction instruction, Processor *processor) {
/* YOUR CODE HERE */
// auipc (add upper imm to PC): rd <-- pc + offset
processor->R[instruction.utype.rd] = processor->PC + (instruction.utype.imm << 12);
processor->PC += 4;
}

void store(Byte *memory, Address address, Alignment alignment, Word value) {
/* YOUR CODE HERE */
if (alignment == LENGTH_BYTE) {
memory[address] = 0xFF & value;

// filling the rest of the bits to fully extend number
/*
int full_number = sign_extend_number(memory[address], 8);
full_number = full_number >> 8;

memory[address + 1] = 0xFF & full_number;
full_number = full_number >> 8;

memory[address + 2] = 0xFF & full_number;
full_number = full_number >> 8;

memory[address + 3] = 0xFF & full_number;
*/

}
else if (alignment == LENGTH_HALF_WORD) {
//int full_number = sign_extend_number((0xFFFF & value), 16);
memory[address] = 0xFF & value;
value = value >> 8;

memory[address + 1] = 0xFF & value;

/*
memory[address] = 0xFF & full_number;
full_number = full_number >> 8;

memory[address + 1] = 0xFF & full_number;
full_number = full_number >> 8;

memory[address + 2] = 0xFF & full_number;
full_number = full_number >> 8;

memory[address + 3] = 0xFF & full_number;
*/

}
// you want to store all 32 bits of the value in the memory, each memory loc can store 1 byte (8 bits)
// storing a word
else if (alignment == LENGTH_WORD) {
memory[address] = 0xFF & value;
value = value >> 8;

memory[address + 1] = 0xFF & value;
value = value >> 8;

memory[address + 2] = 0xFF & value;
value = value >> 8;

memory[address + 3] = 0xFF & value;
}
}

Word load(Byte *memory, Address address, Alignment alignment) {
/* YOUR CODE HERE */
// unsigned or signed??
if (alignment == LENGTH_BYTE) {
return memory[address];
}
else if (alignment == LENGTH_HALF_WORD) {
uint16_t half_word = memory[address];
// adding the upper bits
half_word += memory[address + 1] << 8;
return half_word;
}
// you want to store all 32 bits of the value in the memory, each memory loc can store 1 byte (8 bits)
// storing a word
else if (alignment == LENGTH_WORD) {
uint32_t word = memory[address];
// adding the upper bits
word += memory[address + 1] << 8;
word += memory[address + 2] << 16;
word += memory[address + 3] << 24;
return word;
}
else {
return -1;
}
}

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