Notes

/*=============================================================================*/
static void gic_sgi_isr_00(void)
{
gic_print("===============================================n");
gic_print("======= This is SGI ISR 00 =======n");
gic_print("===============================================n");
gic_ctrl.gic_int_result = GIC_RESULT_0;
}

/*=============================================================================*/
static void gic_sgi_isr_01(void)
{
gic_print("===============================================n");
gic_print("======= This is SGI ISR 01 =======n");
gic_print("===============================================n");
gic_ctrl.gic_int_result = GIC_RESULT_1;
}
/*=============================================================================*/
static void GIC_PPI_22_isr(void)
{
gic_print("=======================================n");
gic_print("===== This is PPI22 ISR =====n");
gic_print("=======================================n");
gic_ctrl.gic_int_result = GIC_RESULT_0;
}
/*=============================================================================*/
static void GIC_PPI_23_isr(void)
{
gic_print("=======================================n");
gic_print("===== This is PPI23 ISR =====n");
gic_print("=======================================n");
gic_ctrl.gic_int_result = GIC_RESULT_1;
}
/*=============================================================================*/
static void GIC_SPI_68_isr(void)
{
gic_print("=======================================n");
gic_print("===== This is SPI68 ISR =====n");
gic_print("=======================================n");
gic_ctrl.gic_int_result = GIC_RESULT_0;
}
/*=============================================================================*/
static void GIC_SPI_71_isr(void)
{
gic_print("=======================================n");
gic_print("===== This is SPI71 ISR =====n");
gic_print("=======================================n");
gic_ctrl.gic_int_result = GIC_RESULT_1;
}


/*=============================================================================*/
gic_ret_t GIC_SAME_PRIORITY_CMP_ID (void)
{
uint32_t rw_data;

gic_print("======== Enter Interrupt Same Priority test =================n");

gic_ctrl.gic_int_result = GIC_NO_INT;
gic_print("n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~n");
gic_print("~~~~~~~~~ SAME PRIORITY: SGI ~~~~~~~n");
gic_print("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~n");
gic_reg_rd_print("REG_GICD_CTLR", REG_GICD_CTLR, &rw_data);
gic_secure_reg_rd_print("REG_GICD_CTLR", REG_GICD_CTLR, &rw_data);
gic_print("nSet 16 SGIs as group-1 interruptsn");
gic_secure_reg_set_bits(REG_GICR_IGROUPR0, 0xFFFF, 0xFFFF);

// Set priority SGI1 > SGI0
gic_print("Set Priority SGI1:0xa0; SGI0:0xa7n");
gicr_write_ipriorityr(GICR_CPU0_BASE_ADDR, GIC_SGI0, 0xa0a7);
gic_reg_rd_print("REG_GICR_IPRIORITYR0", REG_GICR_IPRIORITYR0, &rw_data);
/*
GIC to supports up to 32 priority levels. Bits [2:0] of priority are RAZ/WI.
So, writing priority 0xa0 is same as writing priority 0xa7 -> read-back result: a0.
*/
gic_print("Register for 2 SGIs ! n");
register_irq_handler(GIC_SGI0, (boot_irq_handler_t) gic_sgi_isr_00);
register_irq_handler(GIC_SGI1, (boot_irq_handler_t) gic_sgi_isr_01);

gic_print("nGenerate SGI1 and SGI0 simutaneously by set pendingn");
gic_reg_set_bits(REG_GICR_ISPENDR0, BIT1|BIT0, 0x3);
gic_delay(100);

gic_print("Check if SGI0, with lower ID, happens firstn");
if(gic_ctrl.gic_int_result == GIC_RESULT_0) //same priority, GIC_SGI1 happens first.
return GIC_FAIL;

gic_ctrl.gic_int_result = GIC_NO_INT;
gic_print("n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~n");
gic_print("~~~~~~~~~ SAME PRIORITY: PPI ~~~~~~~n");
gic_print("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~n");

// Set priority SGI1 > SGI0
gic_print("Set Priority GIC_PPI22:0xb5; GIC_PPI23:0xb0n");
gicr_write_ipriorityr(GICR_CPU0_BASE_ADDR, GIC_PPI22, 0xb0b50000);
gic_reg_rd_print("REG_GICR_IPRIORITYR5", REG_GICR_IPRIORITYR5, &rw_data);

gic_print("Register for 2 PPIs ! n");
register_irq_handler(GIC_PPI22, (boot_irq_handler_t) GIC_PPI_22_isr);
register_irq_handler(GIC_PPI23, (boot_irq_handler_t) GIC_PPI_23_isr);

gic_print("nGenerate PPI23 and PPI22 simutaneously by set pendingn");
gic_reg_set_bits(REG_GICR_ISPENDR0, BIT23|BIT22, 0x3);
gic_delay(100);

gic_print("Check if PPI22, with lower ID, happens firstn");
if(gic_ctrl.gic_int_result == GIC_RESULT_0) //same priority, GIC_PPI23 happens first.
return GIC_FAIL;

gic_ctrl.gic_int_result = GIC_NO_INT;
gic_print("n~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~n");
gic_print("~~~~~~~~~ SAME PRIORITY: SPI ~~~~~~~n");
gic_print("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~n");

gic_print("Set Priority GIC_SPI68:0x93; GIC_SPI71:0x90n");
gic_reg_set_bits(REG_GICD_IPRIORITYR17, 0xFF, 0x93);
gic_reg_set_bits(REG_GICD_IPRIORITYR17, 0xFF000000, 0x90);
gic_reg_rd_print("REG_GICD_IPRIORITYR17", REG_GICD_IPRIORITYR17, &rw_data);

gic_print("Set Target List to only CPU0n");
gic_reg_wr(REG_GICD_IROUTER68_lower, 0x0);
gic_reg_wr(REG_GICD_IROUTER71_lower, 0x0);
gic_reg_rd_print("REG_GICD_IROUTER68_lower", REG_GICD_IROUTER68_lower,
&rw_data);
gic_reg_rd_print("REG_GICD_IROUTER68_upper", REG_GICD_IROUTER68_upper,
&rw_data);
gic_reg_rd_print("REG_GICD_IROUTER71_lower", REG_GICD_IROUTER71_lower,
&rw_data);
gic_reg_rd_print("REG_GICD_IROUTER71_upper", REG_GICD_IROUTER71_upper,
&rw_data);

gic_print("Register for 2 SPIs ! n");
register_irq_handler(GIC_SPI68, (boot_irq_handler_t) GIC_SPI_68_isr);
register_irq_handler(GIC_SPI71, (boot_irq_handler_t) GIC_SPI_71_isr);

#if 1
gic_print("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~n");
gic_reg_rd_print("REG_GICD_ISPENDR2", REG_GICD_ISPENDR2, &rw_data);
gic_print("nGenerate SPI71 by set pendingn");
gic_reg_set_bits(REG_GICD_ISPENDR2, BIT7, 0x1);
gic_reg_rd_print("REG_GICD_ISPENDR2", REG_GICD_ISPENDR2, &rw_data);
gic_print("nGenerate SPI68 by set pendingn");
gic_reg_set_bits(REG_GICD_ISPENDR2, BIT4, 0x1);
gic_delay(1000);
gic_reg_rd_print("REG_GICD_ISPENDR2", REG_GICD_ISPENDR2, &rw_data);
gic_print("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~n");
#endif

gic_reg_rd_print("REG_GICD_ISPENDR2", REG_GICD_ISPENDR2, &rw_data);
gic_print("nGenerate SPI71 and SPI68 simutaneously by set pendingn");
gic_reg_set_bits(REG_GICD_ISPENDR2, BIT7|BIT4, 0xF);
gic_delay(1000);

#if 1
gic_print("~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~n");
gic_reg_rd_print("REG_GICD_ISPENDR2", REG_GICD_ISPENDR2, &rw_data);
gic_print("nGenerate SPI71 by set pendingn");
gic_reg_set_bits(REG_GICD_ISPENDR2, BIT7, 0x1);
gic_reg_rd_print("REG_GICD_ISPENDR2", REG_GICD_ISPENDR2, &rw_data);
gic_print("nGenerate SPI68 by set pendingn");
gic_reg_set_bits(REG_GICD_ISPENDR2, BIT4, 0x1);
gic_delay(1000);
gic_reg_rd_print("REG_GICD_ISPENDR2", REG_GICD_ISPENDR2, &rw_data);
#endif

gic_print("Check if SPI68, with lower ID, happens firstn");
if(gic_ctrl.gic_int_result == GIC_RESULT_0) //same priority, GIC_SPI71 happens first.
return GIC_FAIL;

return GIC_OK;
}