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Argv[0] = v; Argv[1] = 7;
Start_addr (hex) = 0x1D02C000
Number Bytes (hex) = 0x00000190
CMD opt (dec) = 7
Protect Enable (dec) = 1
===== Initialization ......
Enable clock for OCM module
Write: CRCSR_OCM_CLKEN [0x1FB8C004] = 0x00000003
Read : CRCSR_OCM_CLKEN [0x1FB8C004] = 0x00000003
Disable Reset OCM module
Write: CRCSR_OCM_SRS [0x1FB8C000] = 0x00000000
Read : CRCSR_OCM_SRS [0x1FB8C000] = 0x00000000
Write: CSR_CFG_MEM_RAM_SHUTDOWN [0x1FB8D070] = 0xFFFFFFFF
Write: CSR_CFG_MEM_RAM_SHUTDOWN [0x1FB8D070] = 0x00000000
Read : CSR_CFG_MEM_RAM_SHUTDOWN [0x1FB8D070] = 0x00000000
Read times : 1
Read : BLOCK_MEM_RDY [0x1FB8D074] = 0xFFFFFFFF
Read : OCM_CRCSR_OCM_SRST [0x1FB8C000] = 0x00000000
Read : OCM_CRCSR_OCM_CLKEN [0x1FB8C004] = 0x00000003
.........................................................
OCM Slave Response timeout
Read : OCM_INT_SLV_TMO [0x1FB8E00C] = 0x00000000
Write: OCM_CFG_SLV_RESP_TMO_CNTR [0x1FB8E004] = 0x0000FFFF
Write: OCM_CFG_MASK_DEV_ERR_RESP [0x1FB8E01C] = 0x00000001
=========================================================
Enable interrupt of OCM
Read: MEMERRINTMSK = 0xFFFFFFFF
Write: MEMERRINTMSK = 0xFFDFFFFF
_DBG_ Mask other interrupts for sure
Read : OCM_DBG_TRIG_INTMASK [0x1FB8D060] = 0xFFFFFFFF
Read : OCM_GLBL_SEC_ERRLMASK [0x1FB8D814] = 0xFFFFFFFF
Read : OCM_GLBL_SEC_ERRHMASK [0x1FB8D81C] = 0xFFFFFFFF
Read : OCM_GLBL_MSEC_ERRLMASK [0x1FB8D824] = 0xFFFFFFFF
Read : OCM_GLBL_MSEC_ERRHMASK [0x1FB8D82C] = 0xFFFFFFFF
Read : OCM_GLBL_DED_ERRLMASK [0x1FB8D834] = 0xFFFFFFFF
Read : OCM_GLBL_DED_ERRHMASK [0x1FB8D83C] = 0xFFFFFFFF
Read : OCM_GLBL_MDED_ERRLMASK [0x1FB8D844] = 0xFFFFFFFF
Read : OCM_GLBL_MDED_ERRHMASK [0x1FB8D84C] = 0xFFFFFFFF
Read : OCM_GLBL_TRANS_ERRMASK [0x1FB8D864] = 0xFFFFFFFF
_DBG_ UnMask time-out interrupts for sure
Write: OCM_INT_SLV_TMOMASK [0x1FB8E010] = 0x00000000
Read : OCM_INT_SLV_TMOMASK [0x1FB8E010] = 0x00000000
Read : OCM_GLBL_ERR_STS [0x1FB8D800] = 0x00000000
Register ocm error interrupt 83
Read : OCM_GLBL_ERR_STS [0x1FB8D800] = 0x00000000
Disable clock of OCM
Write: CRCSR_OCM_CLKEN [0x1FB8C004] = 0x00000002
Access OCM CSRs when OCM clock gate is gate off
_DBG_ ####################################################
_DBG_ ######### This is ISR PERR ########
_DBG_ ####################################################
Read : OCM_INTR_STS [0x1FB8D064] = 0x00000000
Read : OCM_GLBL_ERR_STS [0x1FB8D800] = 0x00000000
Read : OCM_DBG_TRIG_INT [0x1FB8D05C] = 0x00000000
Read : OCM_DBG_TRIG_INTMASK [0x1FB8D060] = 0xFFFFFFFF
Read : OCM_GLBL_SEC_ERRL [0x1FB8D810] = 0x00000000
Read : OCM_GLBL_SEC_ERRLMASK [0x1FB8D814] = 0xFFFFFFFF
Read : OCM_GLBL_SEC_ERRH [0x1FB8D818] = 0x00000000
Read : OCM_GLBL_SEC_ERRHMASK [0x1FB8D81C] = 0xFFFFFFFF
Read : OCM_GLBL_MSEC_ERRL [0x1FB8D820] = 0x00000000
Read : OCM_GLBL_MSEC_ERRLMASK [0x1FB8D824] = 0xFFFFFFFF
Read : OCM_GLBL_MSEC_ERRH [0x1FB8D828] = 0x00000000
Read : OCM_GLBL_MSEC_ERRHMASK [0x1FB8D82C] = 0xFFFFFFFF
Read : OCM_GLBL_DED_ERRL [0x1FB8D830] = 0x00000000
Read : OCM_GLBL_DED_ERRLMASK [0x1FB8D834] = 0xFFFFFFFF
Read : OCM_GLBL_DED_ERRH [0x1FB8D838] = 0x00000000
Read : OCM_GLBL_DED_ERRHMASK [0x1FB8D83C] = 0xFFFFFFFF
Read : OCM_GLBL_MDED_ERRL [0x1FB8D840] = 0x00000000
Read : OCM_GLBL_MDED_ERRLMASK [0x1FB8D844] = 0xFFFFFFFF
Read : OCM_GLBL_MDED_ERRH [0x1FB8D848] = 0x00000000
Read : OCM_GLBL_MDED_ERRHMASK [0x1FB8D84C] = 0xFFFFFFFF
Read : OCM_GLBL_MERR_ADDR [0x1FB8D850] = 0x00000000
Read : OCM_GLBL_MERR_REQINFO [0x1FB8D854] = 0x00000000
Read : OCM_GLBL_TRANS_ERR [0x1FB8D860] = 0x00000000
Read : OCM_GLBL_TRANS_ERRMASK [0x1FB8D864] = 0xFFFFFFFF
Read : OCM_INT_SLV_TMOMASK [0x1FB8E010] = 0x00000000
Read : OCM_INT_SLV_TMO [0x1FB8E00C] = 0x00000000
Write: OCM_INT_SLV_TMO [0x1FB8E00C] = 0x000000FF
ocm_test_val = 0
rite: CRCSR_OCM_CLKEN [0x1FB8C004] = 0x00000003
... Interrupt not occur or timeout
###########################################
#### FAIL ####
###########################################
Shell>
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