Notes

`timescale 1ns / 1ps

module ayarliSayac(
input clk,
input rst,
input etkin,
input ayar_yap,
input[2:0] sayma_miktari,
input sayma_yonu,
output[5:0] out_sayac
);

localparam UP = 1'b0;
localparam DOWN = 1'b1;

reg state = UP, state_next;
reg[2:0] count_step = 3'd1, count_step_next;
reg[5:0] r_counter = 6'd0, r_counter_next;

always@* begin
state_next = state;
count_step_next = count_step;
r_counter_next = r_counter;

if(etkin) begin
case(state)
UP: begin
if((r_counter + count_step) < r_counter)
r_counter_next = 6'b111111;
else
r_counter_next = r_counter + count_step;
end // UP

DOWN: begin
if((r_counter - count_step) > r_counter)
r_counter_next = 6'd0;
else
r_counter_next = r_counter - count_step;
end // DOWN
endcase
end // etkin

if(ayar_yap) begin
state_next = sayma_yonu;
count_step_next = sayma_miktari;
end //ayar_yap

end

always@(negedge clk) begin
if(rst) begin
r_counter <= 6'd0;
state <= UP;
count_step <= 3'd1;
end
else begin
r_counter <= r_counter_next;
state <= state_next;
count_step <= count_step_next;
end
end

assign out_sayac = r_counter;

endmodule